On Wednesday January 23, 2013 the Rochester Explorer's Scout Post sponsored by the Rochester Engineering Society came to visit Microelectronic Engineering. The students (and some parents too!) got to gown-up and process some souvenir wafers in our cleanroom. Dr. Karl Hirschman had given them a presentation the previous week. On Wednesday Dr. Hirschman, Dr. Pearson and graduate students, Tarun Mudgal, Seth Slavin, Qinlong Li, and Chris O'Connel (Comp. Sci undergraduate student). As you can see below we had quite a few people working away in the clean-room. On the left a group of students is looking a the monitor to see an image through the microscope of some integrated circuits fabricated at RIT. On the right, students and parents are waiting to develop the image they exposed into photoresist on on their wafer
Here is a picture one of the finished wafers with the RES log and RIT logos (not sure why it comes out upside down??)
If anyone who attended has pictures to share please contact Dr. Hirschman.
RITmicro fabrication lab 502
Thursday, January 24, 2013
In Lab on Tuesday 1/22/2013 half of the students did boron channel-stop implants under the future Field Oxide regions of our nMOSFET wafers. Here you see the 150mm wafer end station (the 100 mm end station is off to the right). The source enclosure is in the back of the two students and one of the control racks is on the left.
This picture shows Joshua and Matt setting up the beam.
Here we see them adjusting the current display and setting up the "M" shape of the properly focused and trimmed beam.
The resist was stripped off using our hot solvent strip and the wafers were put through the Standard Clean process (see below). Don't worry there was another student in protective gear backing up Matt. Josh was just observing.
We then set up the Bruce oxidation furnace recipe for the Field Oxide (FOX) growth. We used recipe #xxx. The recipe details are listed on the RIT MyCourses website. You have to be registered for the course to access those details or email Dr. Pearson.
A view of 4 of the furnace tubes.
This picture shows Joshua and Matt setting up the beam.
Here we see them adjusting the current display and setting up the "M" shape of the properly focused and trimmed beam.
The resist was stripped off using our hot solvent strip and the wafers were put through the Standard Clean process (see below). Don't worry there was another student in protective gear backing up Matt. Josh was just observing.
We then set up the Bruce oxidation furnace recipe for the Field Oxide (FOX) growth. We used recipe #xxx. The recipe details are listed on the RIT MyCourses website. You have to be registered for the course to access those details or email Dr. Pearson.
A view of 4 of the furnace tubes.
Tuesday, January 22, 2013
Processing of split CMOS Polygate FETs
In the RIT MicroE 632/702 lab on Thursday Jan 17th 2013 we continued with the processing of our split CMOS polygate FET fabrication process. We call it split CMOS because of the fact that for our simplified process we have nFETs on some wafers and pFETS on other wafers and only look at each type individually.
The first step in our process was to do level zero lithography for global alignment marks on our wafer for use with our ASML i-line stepper. This litho step places six small patterns (2 columns of three) used for alignment on the wafer.
Level zero alignmark
After this litho step the pattern was etched into the silicon using a radio frequency plasma of SF6 gas. The marks will be used for alignment of subsequent mask layers. Shown below is part of the mask set designed by Dr. Karl Hirschman and his "strong-arm" research team, including Brian Silkey. There are capacitor structures in the upper right corner.
Hirschman research group logo and GCA alignment mark.
Here is a picture of Qinlong running the 150mm coat and develop line to coat the wafers with photoresist.
Here is a shot of the set-up screen for the LAM 490 etcher
We loaded the wafers and ran the tool. Here is Dr. Hirschman checking out the progress.
Here is a screen shot of the optical end-point detector signals versus time during the plasma etch run. The signal intensity changes slightly when the etching process get through the polysilicon and starts etching the underlying oxide (etches more slowly). The last change is when the etch breaks through the 150 Angstroms of gate oxide and starts etching the silicon.
Etch time was 2 minutes and 30 seconds
The first step in our process was to do level zero lithography for global alignment marks on our wafer for use with our ASML i-line stepper. This litho step places six small patterns (2 columns of three) used for alignment on the wafer.
Level zero alignmark
After this litho step the pattern was etched into the silicon using a radio frequency plasma of SF6 gas. The marks will be used for alignment of subsequent mask layers. Shown below is part of the mask set designed by Dr. Karl Hirschman and his "strong-arm" research team, including Brian Silkey. There are capacitor structures in the upper right corner.
Hirschman research group logo and GCA alignment mark.
Here is a photomicrograph of one of the capacitor structures
We were also etching polysilicon capacitors in the LAM 490 plasma etcher for another experiment that we are doing in this lab. Shown below is one of the capacitor wafers after the SF6 etch.
Here is a shot of the set-up screen for the LAM 490 etcher
We loaded the wafers and ran the tool. Here is Dr. Hirschman checking out the progress.
Here is a screen shot of the optical end-point detector signals versus time during the plasma etch run. The signal intensity changes slightly when the etching process get through the polysilicon and starts etching the underlying oxide (etches more slowly). The last change is when the etch breaks through the 150 Angstroms of gate oxide and starts etching the silicon.
Etch time was 2 minutes and 30 seconds
Thursday, January 17, 2013
Just getting started
This is the first post in a new blog about the laboratory sections for the Silicon Processes and Microelectronics II classes at RIT in the winter quarter of 2012-2013.
I want to acknowledge Dr. Ivan Puchades who motivated me to try this. Please see his MEMSlab blog.
memslab.blogspot.com
We are part way through the quarter so I am not sure if we will be able to go back and make up for all the missed posts.
I want to acknowledge Dr. Ivan Puchades who motivated me to try this. Please see his MEMSlab blog.
memslab.blogspot.com
We are part way through the quarter so I am not sure if we will be able to go back and make up for all the missed posts.
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