Processing of split CMOS Polygate FETs

In the RIT MicroE 632/702 lab on Thursday Jan 17th 2013 we continued with the processing of our split CMOS polygate FET fabrication process. We call it split CMOS because of the fact that for our simplified process we  have nFETs on some wafers and pFETS on other wafers and only look at each type individually.

The first step in our process was to do level zero lithography for global alignment marks on our wafer for use with our ASML i-line stepper. This litho step places six small patterns (2 columns of three) used for alignment on the wafer.

                                                                 Level zero alignmark

After this litho step the pattern was etched into the silicon using a radio frequency plasma of SF6 gas. The marks will be used for alignment of subsequent mask layers. Shown below is part of the mask set designed by Dr. Karl Hirschman and his "strong-arm" research team, including Brian Silkey. There are capacitor structures in the upper right corner.

Hirschman research group logo and GCA alignment mark.

Here is a picture of Qinlong running the 150mm coat and develop line to coat the wafers with photoresist.

Here is a photomicrograph of one of the capacitor structures

We were also etching polysilicon capacitors in the LAM 490 plasma etcher for another experiment that we are doing in this lab. Shown below is one of the capacitor wafers after the SF6 etch.

Here is a shot of the set-up screen for the LAM 490 etcher

We loaded the wafers and ran the tool. Here is Dr. Hirschman checking out the progress.

Here is a screen shot of the optical end-point detector signals versus time during the plasma etch run. The signal intensity changes slightly when the etching process get through the polysilicon and starts etching the underlying oxide (etches more slowly). The last change is when the etch breaks through the 150 Angstroms of gate oxide and starts etching the silicon.

Etch time was 2 minutes and 30 seconds